With the rapid development of microelectronics technology, feature sizes of integrated circuits keep scaling down, leading to ever increasing interconnection density. In the meantime, consumer demand for higher performance and lower power consumption keeps rising as well. The traditional approach of further reducing line width of interconnections to improve circuit performance is already being limited by physical properties of the materials and equipment knowhow. For example, the resistance and capacitance delay of a 2D interconnection line gradually becomes the bottleneck of performance improvement of semiconductor chips. To deal with this predicament, the concept of 3D interconnection has been put forward and through silicon via (TSV) technology has become an appealing solution recently, which can realize 3D interconnection between wafers (or chips) or between a chip and a substrate by producing vertical metal columns in wafers with metal bumps. Such 3D interconnect structures can substantially tackle the limitations of traditional 2D wiring of semiconductor chips. Compared with the traditional stacking techniques including wafer bonding, TSV interconnection method has increased 3D stacking density and reduced packaging dimension, thus greatly improving the speed of a packaged chip and reducing its power consumption. Therefore, TSV technology is widely regarded as one of the key solutions for high density packaging in the future.
TSV is a technique by which vertical via holes are formed between chips or between wafers, and a conductive material is deposited in the vertical via holes (e.g., by electroplating) to realize interconnection in three dimensions. Specifically, after thinning the back surface of the wafer, a top portion (or tip) of the conductive metal in each TSV is exposed from the substrate, and then bumps are formed on the exposed tip. These bumps can be both electrically and mechanically connected with the corresponding bumps (i.e., solder bumps) on adjacent, prefabricated substrates or chips. High-density packaging led to the requirement for fine-pitch bumping technology. Especially in image sensor and 2.5D/3D chip integration area, fine-pitch micro-bumps are indispensable. For example, high-end image sensors featuring a large pixel count, high resolution, and finer pitch between pixels typically require the same level of fine pitch for micro-bumps. Prior micro-bump fabrication process consists of such steps as seed layer deposit, photoresist, lithography, electroplating, and seed layer etching, all these processes except seed layer deposit can affect the pitch of the micro-bumps. In particular, the seed layer etching step brings with it the problem of undercut which can significantly affect the working life of the resulting micro-bumps.
Moreover, with the existing micro-bump technology, it is through a solder ball that the bump tip makes contact with a pad of a corresponding device. However, with the ever decreasing pitch between bumps, the risk of a short circuit happening between solder balls and the adjoining pads already increases to such a level that the device safety will be sacrificed.
A technical solution for the aforementioned problem has not been found in prior art.